Silicon Labs Introduces Industry's Broadest Portfolio for 56G/112G SerDes Clocking
AUSTIN, Texas, June 25, 2018 /PRNewswire/ -- Silicon Labs (NASDAQ: SLAB) has expanded its timing portfolio to meet the high-performance clocking requirements of 56G PAM-4 SerDes and emerging 112G serial applications.
- AUSTIN, Texas, June 25, 2018 /PRNewswire/ -- Silicon Labs (NASDAQ: SLAB) has expanded its timing portfolio to meet the high-performance clocking requirements of 56G PAM-4 SerDes and emerging 112G serial applications.
- Silicon Labs is the first timing supplier to provide fully integrated clock IC solutions for 56G designs that integrate SerDes, CPU and system clocks into a single device.
- "Silicon Labs' new clock generators, jitter attenuators and VCXO/XOs comprise the industry's broadest portfolio of frequency-flexible, ultra-low-jitter timing devices for the latest 56G SerDes-based 100/200/400/600G communications and data center designs," said James Wilson, Senior Marketing Director for Silicon Labs' timing products.
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