CAES Receives Contract from Vinnova to Advance High Performance RISC-V Space Computing
The new NOEL-V fault-tolerant, 64-bit processor core is based on the open RISC-V instruction set architecture and builds upon CAES heritage with the SPARC/LEON architecture.
- The new NOEL-V fault-tolerant, 64-bit processor core is based on the open RISC-V instruction set architecture and builds upon CAES heritage with the SPARC/LEON architecture.
- It marks the newest addition to CAES trusted fault tolerant space computing product portfolio.
- We look forward to working with Vinnova and our project partners to enhance our RISC-V processor technology to meet our customers next generation space program needs, said Mike Kahn, President and CEO of CAES.
- The results of this initiative with Vinnova will inform our future radiation-hardened NOEL-V microprocessor development in collaboration with the European Space Agency, said Sandi Habinc, General Manager of Gaisler Products, CAES.