MIPS


Associated tags: MIPS, RISC, IP, CPU, SAN, SOC, ADAS, OOO, Software, Video game console

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MIPS Named Embedded Award Nominee for eVocore P8700 Multiprocessor

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Tuesday, February 28, 2023
SME, OOO, Exhibition, ADAS, Security, RISC, CPU, Embedded, MIPS, SAN, SOC, Conference, Artificial intelligence, Original equipment manufacturer, IP, Consumer electronics, Mobile phone, Software

SAN JOSE, Calif., Feb. 28, 2023 /PRNewswire/ -- MIPS, a leading developer of highly scalable RISC processor IP,  has been named an Embedded Award nominee for the company's eVocore (™) P8700 multiprocessor system, the industry's most scalable RISC-V CPU IP core.

Key Points: 
  • SAN JOSE, Calif., Feb. 28, 2023 /PRNewswire/ -- MIPS , a leading developer of highly scalable RISC processor IP,  has been named an Embedded Award nominee for the company's eVocore (™) P8700 multiprocessor system, the industry's most scalable RISC-V CPU IP core.
  • As part of the Embedded World Conference and Exhibition in Nuremberg, Germany, the annual Embedded Awards honor global innovations in the field of embedded systems technologies.
  • "MIPS is thrilled to be nominated for this esteemed award alongside some of the brightest innovators in the industry," Desi Banatao, MIPS CEO.
  • Applications came from many start-ups, small and large SMEs and from some major corporations,"
    MIPS will demonstrate the P8700 during Embedded World at the RISC-V booth - 4A-620.

MIPS Partners With Mobileye to Accelerate Next Generation Autonomous Driving Technologies and Advanced Driver Assistance Systems

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Tuesday, December 13, 2022
EyeQ, IP, Partnership, ISA, ADAS, Intel, OOO, RISC, Central processing unit, CPU, Growth, Multimedia, MIPS, USD, Video game console, Mobile phone, Satellite navigation device, Kerosene, Mobileye, SOC, Engineering

SAN JOSE, Calif. , Dec. 12, 2022 /PRNewswire/ -- MIPS, a leading developer of highly scalable RISC processor IP, announced it is continuing its partnership with Mobileye, in accelerating innovation in autonomous driving technologies and advanced driver-assistance systems (ADAS).

Key Points: 
  • "Mobileye's highly efficient, scalable and proven EyeQ SoCs are driving a revolution in driver assistance and autonomous vehicle technologies.
  • Mobileye is using MIPS' processors in several of the EyeQ generations, starting with the EyeQ2, including EyeQ6H, EyeQ6L and now the next-generation EyeQ.
  • "Mobileye is a pioneer in advanced driver assistance systems and is an innovator in autonomous vehicles, and we are thrilled to continue our long-time partnership in driving the future of next-generation chips for autonomous vehicles."
  • MIPS and the MIPS logo are trademarks or registered trademarks MIPS Tech LLC in the United States and other countries.

MIPS Announces Availability of its first RISC-V IP core - the eVocore P8700 Multiprocessor

Retrieved on: 
Tuesday, December 13, 2022
Internal, EyeQ, Software, Ecosystem, IP, Radar, ADAS, ISO, OOO, Lidar, RISC, Original equipment manufacturer, AV, Central processing unit, CPU, SOC, Multimedia, MIPS, Safety, SAN, Socs, IVI, HPC, Video game console, Conveyor system, Mobileye, Engineering

SAN JOSE, Calif. , Dec. 12, 2022 /PRNewswire/ -- As the shift toward RISC-V accelerates across industries, the open standard instruction set architecture (ISA) is ushering a new wave of innovation and collaboration. In an effort to help fuel this trend, MIPS, a leading developer of highly scalable RISC processor IP, has announced availability of the eVocore (™) P8700, the industry's highest performance, most scalable RISC-V multiprocessor IP. The P8700 has already been licensed for applications including automotive driver assistance systems (ADAS) and autonomous driving.

Key Points: 
  • In an effort to help fuel this trend, MIPS , a leading developer of highly scalable RISC processor IP, has announced availability of the eVocore () P8700, the industry's highest performance, most scalable RISC-V multiprocessor IP.
  • The eVocore P8700 multiprocessor IP core, which includes best-in-class performance efficiency for use in Software-on-a-Chip (SoC) applications, is one of the first MIPS products based on the RISC-V open ISA.
  • "The eVocore family of IP cores including the P8700 represents the continuing evolution of MIPS as we fully embrace RISC-V," said Desi Banatao, MIPS CEO.
  • We believe that our RISC-V P8700 multiprocessor core will help make it possible for companies of all sizes to get to market quickly with innovative SoC solutions."

Intel Taps MIPS eVocore for Intel Pathfinder for RISC-V

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Tuesday, August 30, 2022
COO, Machine learning, Dado Banatao, Intel, Functional safety, SAN, ISA, Solution, IDE, Automotive industry, MIPS, Pathfinder, Architecture, IP, RISC, Name, Fusa, Industry, Adoption, Efficiency, Video game console, SOC

SAN JOSE, Calif., Aug. 30, 2022 /PRNewswire/ -- MIPS, a leading developer of highly scalable RISC processor IP, announced it is working with Intel to accelerate innovation in open computing. As part of this effort, MIPS' eVocore is being incorporated into the new Intel® Pathfinder for RISC-V*, a platform designed to deliver new capabilities for pre-silicon development. Intel® Pathfinder allows new ways for System-on-a-Chip (SoC) architects and system software developers to define new products and pursue pre-silicon software development on RISC-V.

Key Points: 
  • As part of this effort, MIPS' eVocore is being incorporated into the new Intel Pathfinder for RISC-V*, a platform designed to deliver new capabilities for pre-silicon development.
  • The Intel Pathfinder FPGA development platform incorporates MIPS cores within a unified IDE, while supporting leading operating systems and industry-standard toolchains.
  • * Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.
  • **MIPS and the MIPS logo are trademarks or registered trademarks of MIPS Tech LLC in the United States and other countries.

Americans Fall Short in Concussion Education and Prevention, New Survey Commisioned by Mips Reveals

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Thursday, June 2, 2022
National Center for Telehealth & Technology, Korea Disease Control and Prevention Agency, Death, Skiing, Head, Nielsen, Mortality, Concussion, Head Injuries, Centers for Disease Control and Prevention, Tennis, LINK, Brain damage, Sport, Child, Team, Diffuse axonal injury, CDC, Female, FIM, TBI, Center, Male, Risk, Brain, Prevalence, National Center for Health Statistics, Education, Safety, Medical statistics, Sports equipment, Personal protective equipment, Americans, EU, MIPS

STOCKHOLM, June 2, 2022 /PRNewswire/ -- A new survey suggests a large disconnect in Americans' education around concussions and how to reduce the risk of them using helmets.

Key Points: 
  • In the United States, the prevalence of traumatic brain injuries (TBI), especially in sports, has been called a crisis.
  • The survey, which was conducted by Nielsen , a consumer survey company, and commissioned by Mips , a helmet safety technology company, polled a representative sample of 1,000 Americans, split evenly between male and female, ranging 18-65 years old.
  • Among the most significant findings of the survey is that 70 percent of American helmet buyers are unaware of the term rotational motion.
  • Rotational motion is a common cause for concussions and more severe brain injuries in oblique hits to the head.

MIPS Pivots to RISC-V with Best-In-Class Performance and Scalability

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Tuesday, May 10, 2022
L2, AV, IVI, CPU, Lists of people executed in the United States, Coherence, Environment, RISC, ISA, Leadership, Adoption, ADAS, Efficiency, MIPS, Memory, Traction, CAGR, IP, Solution, ASIC, Socs, CEO, SAN, OOO, Growth, Central processing unit, SOC, Video game console, Computer data storage

SAN JOSE, Calif., May 10, 2022 /PRNewswire/ -- MIPS, a leading developer of highly scalable RISC processor IP, announces its entrance to the RISC-V market, previewing the first products in its eVocore™ product lineup. The new eVocore P8700 and I8500 multiprocessor IP cores are the first MIPS products based on the RISC-V open instruction set architecture (ISA) standard.  

Key Points: 
  • eVocore products are designed to extend MIPS' leadership in high-performance, real-time compute applications such as networking, datacenter, and automotive.
  • "With this transition to RISC-V, MIPS is targeting the high-performance segment of the processor market," states MIPS CEO Desi Banatao.
  • MIPS is bringing to the RISC-V community a heritage of CPU innovation and new RISC-V compatible CPUs designed for flexibility and scalability."
  • MIPS and the MIPS logo are trademarks or registered trademarks MIPS Tech LLC in the United States and other countries.

MIPS Chooses Ashling’s RiscFree™ Toolchain for its RISC-V ISA Compatible IP Cores

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Monday, March 28, 2022
Data Management, Security, Technology, Software, Networks, Internet, Adoption, IDE, Engineering, FPGA, Simulation, MIPS, Socs, OpenPOWER Foundation, Linux, CEO, Compiler, ARC, Ides, Ecosystem, RISC, Solution, MCU 8051 IDE, Awareness, GCC, ISA, 3D printing, Video game console, Audit, Ashling, ASHLING, MIPS, RISC-V

Ashling and MIPS announced today that Ashlings RiscFree Toolchain has been extended to support MIPS RISC-V ISA based IP cores.

Key Points: 
  • Ashling and MIPS announced today that Ashlings RiscFree Toolchain has been extended to support MIPS RISC-V ISA based IP cores.
  • RiscFree is Ashlings Integrated Development Environment (IDE) including a compiler and debugger for RISC-V based development, and it now has support for MIPS RISC-V ISA based IP cores, enhanced by MIPS own proven and tested Core Framework Platform.
  • We are delighted to have Ashling RiscFree support for our RISC-V ISA IP cores.
  • The Ashling RiscFree toolchain will include support for both code development and debug on MIPS RISC-V IP cores and includes advanced features such as multi-core and multi-cluster support, Linux debug awareness, real-time trace support, and cache awareness.

Wave Computing and MIPS Emerge from Chapter 11 Bankruptcy

Retrieved on: 
Monday, March 1, 2021
Instruction set architectures, Computer architecture, MIPS Technologies, Advanced RISC Computing, Computing, Computers, Microcontrollers, RISC-V, MIPS architecture, Reduced instruction set computer, MIPS architecture processors

SANTA CLARA, Calif., March 1, 2021 /PRNewswire/ --Wave Computing, Inc. ("Wave") and its subsidiaries including MIPS Tech, the processor technology company focused on the commercialization of RISC-based processor architectures and IP cores, today emerged from Chapter 11 bankruptcy protection.

Key Points: 
  • SANTA CLARA, Calif., March 1, 2021 /PRNewswire/ --Wave Computing, Inc. ("Wave") and its subsidiaries including MIPS Tech, the processor technology company focused on the commercialization of RISC-based processor architectures and IP cores, today emerged from Chapter 11 bankruptcy protection.
  • MIPS is developing a new industry-leading standards-based 8th generation architecture, which will be based on the open source RISC-V processor standard.
  • The emergence follows the approval of the Company's Chapter 11 plan of reorganization on February 10 by the United States Bankruptcy Court for the Northern District of California.
  • "Now that we have completed our Chapter 11 restructuring, I'm looking forward to growing our business and executing on our go-forward strategy," said Mr. Kohli.