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Fraunhofer IESE Partners With Arteris To Accelerate Advanced Network-on-chip Architecture Development for AI/ML Applications

Retrieved on: 
Tuesday, October 17, 2023
IP, DRAM, AIP, AI, Arteris, Temperature, Environment, Nizar Dramsy, Network on a chip, Architecture, SOC, Research, Computer data storage, Fraunhofer

The interoperability will improve performance, reduce cost and accelerate the schedule of advanced DRAM-centric NoC development for mutual customers.

Key Points: 
  • The interoperability will improve performance, reduce cost and accelerate the schedule of advanced DRAM-centric NoC development for mutual customers.
  • The interoperability between Arteris and Fraunhofer IESE technology enables designers to complete a thorough performance analysis in the context of DRAM architectures before committing to a NoC architecture.
  • The performance and flexibility of Arteris interconnect IP products support ultra-high bandwidth traffic to feed data to advanced memory architectures supported by the Fraunhofer IESE memory exploration framework," said Frank Schirrmeister, vice president solutions and business development at Arteris.
  • “This collaboration is a positive step forward for designers everywhere.”
    The integration of Arteris and Fraunhofer offerings is available today.