Network on a chip

Arteris Expands Ncore Cache Coherent Interconnect IP To Accelerate Leading-Edge Electronics Designs

Retrieved on: 
Wednesday, March 13, 2024
Cortex, Arm, Certification, Mobileye, ACE, Acceleration, Memory, Network on a chip, ASIL, ASIL D, Architecture, AIP, Arteris, IP, AXI, Safety, Security, ISO, Engineering, IPS, Video game

CAMPBELL, Calif., March 13, 2024 (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced the immediate availability of the latest release of Ncore cache coherent network-on-chip (NoC) IP. Ncore ensures low latency integration of hardware accelerators into a coherent domain, enabling the speed and efficiency required for cutting-edge applications in complex SoC designs. Deploying Ncore can save SoC design teams upwards of 50 years of engineering effort per project compared to manually generated interconnect solutions.

Key Points: 
  • CAMPBELL, Calif., March 13, 2024 (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced the immediate availability of the latest release of Ncore cache coherent network-on-chip (NoC) IP.
  • Ncore ensures low latency integration of hardware accelerators into a coherent domain, enabling the speed and efficiency required for cutting-edge applications in complex SoC designs.
  • Deploying Ncore can save SoC design teams upwards of 50 years of engineering effort per project compared to manually generated interconnect solutions.
  • Ncore cache coherent interconnect IP is an ideal companion to FlexNoC, Arteris’ industry-leading non-coherent interconnect IP.

Achronix FPGAs Add Support for Bluespec’s Linux-capable RISC-V Soft Processors to Enable Scalable Processing

Retrieved on: 
Tuesday, March 26, 2024
Software, Networks, Hardware, Electronic Design Automation, Artificial Intelligence, Data Management, Technology, Semiconductor, Socs, 2D, Network on a chip, Product planning, Field-programmable gate array, Architecture, IP, Multimedia, Family, FPGA, Silicon, Video game

Marking an industry first, Bluespec’s RISC-V processors now seamlessly integrate into the Achronix 2D network-on-chip (NoC) architecture, simplifying integration and enabling engineers to add scalable processing to their Achronix FPGA designs easily.

Key Points: 
  • Marking an industry first, Bluespec’s RISC-V processors now seamlessly integrate into the Achronix 2D network-on-chip (NoC) architecture, simplifying integration and enabling engineers to add scalable processing to their Achronix FPGA designs easily.
  • View the full release here: https://www.businesswire.com/news/home/20240326156616/en/
    Achronix FPGAs support Bluespec RISC-V soft IP cores for scalable processing.
  • “The company’s Linux-capable RISC-V soft processors, paired with our high-performance and high-density FPGAs, help our customers differentiate their products and get to market faster.”
    To learn more about Bluespec’s RISC-V soft processors for Achronix FPGAs, please visit: https://info.bluespec.com/achronix .
  • Contact Achronix for more information on how the Achronix and Bluespec collaboration can revolutionize your FPGA projects with Linux-capable RISC-V soft processors optimized for Achronix Speedster7t FPGAs: https://go.achronix.com/bluespec-achronix-risc-v-fpgas .

EdgeQ Deploys Arteris IP for its 5G+AI Base Station-on-a-Chip for Wireless Infrastructure

Retrieved on: 
Tuesday, February 13, 2024
LTE, Architecture, Artificial intelligence, AI, Network on a chip, Communication, Base station, AIP, Arteris, IP, SOC, Video game

CAMPBELL, Calif., Feb. 13, 2024 (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced that EdgeQ has deployed Arteris’ FlexNoC network-on-chip (NoC) IP on its revolutionary 5G and AI-driven Base Station-on-a-Chip.

Key Points: 
  • CAMPBELL, Calif., Feb. 13, 2024 (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced that EdgeQ has deployed Arteris’ FlexNoC network-on-chip (NoC) IP on its revolutionary 5G and AI-driven Base Station-on-a-Chip.
  • The scalable and adaptive EdgeQ platform targets communications for both small-cell and macro-cell applications in a software-defined manner.
  • This scalable architecture packs high throughput performance across a large set of concurrent users, within a compact power envelope.
  • The company’s approach is to offer an all-in-one chip that delivers multi-mode 4G and 5G convergence along with artificial intelligence.

Arteris Selected by Rain AI for Use in the Next Generation of AI

Retrieved on: 
Tuesday, January 30, 2024
AIP, Graphics processing unit, AI, Arteris, Machine learning, Synthetic media, SOC, Artificial intelligence, ISA, Generative, IP, Algorithm, Software, Network on a chip, Medical device

Arteris' FlexNoC 5, connecting a mesh topology for high-density AI computing, will enable Rain AI to achieve optimal performance at a lower cost of operation.

Key Points: 
  • Arteris' FlexNoC 5, connecting a mesh topology for high-density AI computing, will enable Rain AI to achieve optimal performance at a lower cost of operation.
  • Creating a future with abundant and scalable artificial intelligence is critical for the AI revolution," said William Passo, CEO of Rain AI.
  • Rain AI is on a mission to build the compute platform for the future of AI, including training and inference on the same platform to enable scale on-device AI.
  • Arteris remains steadfast in its commitment to delivering state-of-the-art system IP products, empowering innovators like Rain AI to achieve groundbreaking advancements in semiconductor technology.

OpenHW Group Announces CORE-V CVA6 Platform Project for RISC-V Software Development & Testing

Retrieved on: 
Tuesday, November 7, 2023
Semiconductor, Hardware, Electronic Design Automation, Technology, Software, UCSB, Software engineering, SW, Assistant, FPGA, Platform, BSC, IDE, Environment, Princeton University, Compiler, Logic, SDK, Ecosystem, Xilinx, AWS, Safety, Amazon, Red Hat, Communication, Digilant, Memory, Silicon, Network on a chip, CI, Video game, Cryptocurrency, Ashling, Thales of Miletus

Today, at the RISC-V Summit, the OpenHW Group announced the multi-member CORE-V CVA6 Platform project .

Key Points: 
  • Today, at the RISC-V Summit, the OpenHW Group announced the multi-member CORE-V CVA6 Platform project .
  • The platform is an open-source FPGA-based software development and testing environment for RISC-V processors designed to provide a vendor-neutral environment for RISC-V software CI and testing that keeps pace with RISC-V standards.
  • We’re pleased to work with other industry leaders on the CORE-V CVA6 Platform project as we collectively work to make the platform an ideal location for RISC-V software testing and development,” stated Hugh Brock, Director, Software Engineering, Red Hat.
  • "As a leading contributor to the RISC-V evolution and leaders of the CVA6 core project within the OpenHW community, we believe the CORE-V CVA6 Platform will accelerate community efforts on RISC-V compliance and software development.

Semidynamics and Arteris Partner To Accelerate AI RISC-V System-on-Chip Development

Retrieved on: 
Thursday, November 2, 2023
Intelligence, HPC, Chiplet, AIP, Artificial intelligence, Partnership, Machine learning, Vector Unit, SOC, AI, CMO, IP, Network on a chip, Arteris, Mobile phone, Computer data storage, Video game

CAMPBELL, Calif., Nov. 02, 2023 (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation and Semidynamics, a provider of fully customizable high bandwidth and high-performance RISC-V processor IP, today announced a partnership to accelerate electronic product innovation for artificial intelligence (AI), machine learning (ML) and high-performance computing (HPC) applications.

Key Points: 
  • Arteris and Semidynamics partnership enhances the flexibility and highly configurable interoperability of RISC-V processor IP with system IP.
  • The partnership supports the interoperability between Semidynamics' Atrevido™ and Avispado™ 64-bit RISC-V processor IP cores and Arteris’ Ncore cache coherent network-on-chip (NoC) system IP.
  • Partnering to pre-integrate with Arteris' Ncore cache coherent technology will result in accelerated project schedules for our mutual customers."
  • The partnership currently focuses on a demonstrator design integrating a Semidynamics’ four-core RISC-V cluster using Arteris’ Ncore cache coherent NoC technology.

Fraunhofer IESE Partners With Arteris To Accelerate Advanced Network-on-chip Architecture Development for AI/ML Applications

Retrieved on: 
Tuesday, October 17, 2023
IP, DRAM, AIP, AI, Arteris, Temperature, Environment, Nizar Dramsy, Network on a chip, Architecture, SOC, Research, Computer data storage, Fraunhofer

The interoperability will improve performance, reduce cost and accelerate the schedule of advanced DRAM-centric NoC development for mutual customers.

Key Points: 
  • The interoperability will improve performance, reduce cost and accelerate the schedule of advanced DRAM-centric NoC development for mutual customers.
  • The interoperability between Arteris and Fraunhofer IESE technology enables designers to complete a thorough performance analysis in the context of DRAM architectures before committing to a NoC architecture.
  • The performance and flexibility of Arteris interconnect IP products support ultra-high bandwidth traffic to feed data to advanced memory architectures supported by the Fraunhofer IESE memory exploration framework," said Frank Schirrmeister, vice president solutions and business development at Arteris.
  • “This collaboration is a positive step forward for designers everywhere.”
    The integration of Arteris and Fraunhofer offerings is available today.

Arteris Interconnect IP Deployed in NeuReality Inference Server for Generative AI and Large Language Model Applications

Retrieved on: 
Tuesday, October 10, 2023
IP, Deep learning, Machine learning, AIP, AI, LLM, Arteris, Running, Microprocessor, NR1, Generative, Synthetic media, Network on a chip, Software, Central processing unit, Graphics processing unit, SOC, Medical device

This integration is architected in an 8-hierarchy NoC with an aggregated bandwidth of 4.5TB/sec, meeting low latency requirements for running AI applications at scale and lower cost.

Key Points: 
  • This integration is architected in an 8-hierarchy NoC with an aggregated bandwidth of 4.5TB/sec, meeting low latency requirements for running AI applications at scale and lower cost.
  • The NeuReality inference server targets Generative AI, Large Language Models (LLMs) and other AI workloads.
  • “The new era of Generative AI with LLMs requires large-scale computing that is faster, easier, and less expensive.
  • “We are thrilled to be working with NeuReality, and deploying Arteris IP to provide AI connectivity, supporting their vision of cost-effective, high-performance AI at scale.”

Arteris Wins Autonomous Vehicle Technology of the Year Award

Retrieved on: 
Thursday, October 5, 2023
Connected car, Machine learning, AIP, AI, Arteris, Transport, Electronics, ADAS, Socs, Network on a chip, Miniature Sensor Technology Integration-3, SOC, Okinawa Autotech, Video game, Mobile phone

Arteris won the Autonomous Vehicle Technology of the Year award for its latest system IP innovation, announced earlier this year.

Key Points: 
  • Arteris won the Autonomous Vehicle Technology of the Year award for its latest system IP innovation, announced earlier this year.
  • “Arteris technology is accelerating the development of advanced automotive SoCs for design teams across the globe,” said Bryan Vaughn, managing director of AutoTech Breakthrough Awards.
  • “Automotive industry innovation continues unabated, pushing the envelope on underlying electronics needed for AI and machine learning autonomous driving SoCs,” said Michal Siwinski, chief marketing officer of Arteris.
  • “Delivering physically aware NoC IP helps our customers predictably design and deploy such chips on schedule, spec and budget.

Achronix Announces FPGA-Powered Accelerated Automatic Speech Recognition Solution

Retrieved on: 
Wednesday, October 11, 2023
IP, GPU, Algorithm, Partnership, Achronix, AI, MLP, ASR, OPEX, EE Times, Field-programmable gate array, Network on a chip, Architecture, CPU, 99th Infantry Division (United States), Capital expenditure, PyTorch, ML, Video game, Cryptocurrency, FPGA

SANTA CLARA, Calif., Oct. 11, 2023 /PRNewswire/ -- Achronix Semiconductor Corporation, a leader in high-performance FPGAs and embedded FPGA (eFPGA) IP, is proud to announce its latest innovation in partnership with Myrtle.ai — an accelerated automatic speech recognition (ASR) solution based on the Speedster7t FPGA. This transformative solution converts spoken language to text in over 1,000 concurrent real-time streams with high accuracy and fast response times while delivering up to a 20 times improvement in performance over competing solutions. Achronix will demonstrate this solution at the upcoming SC23 conference in Denver on November 12-17, 2023, at booth 2019.

Key Points: 
  • SANTA CLARA, Calif., Oct. 11, 2023 /PRNewswire/ -- Achronix Semiconductor Corporation, a leader in high-performance FPGAs and embedded FPGA (eFPGA) IP, is proud to announce its latest innovation in partnership with Myrtle.ai — an accelerated automatic speech recognition (ASR) solution based on the Speedster7t FPGA.
  • Achronix will demonstrate this solution at the upcoming SC23 conference in Denver on November 12-17, 2023, at booth 2019.
  • The Achronix-Myrtle.ai accelerated ASR solution will have a revolutionary impact on industries that depend on rapid and accurate speech-to-text conversion.
  • Evaluate the solution today with your own data set and schedule a detailed discussion and demonstration with our team: Contact Achronix and review our ASR solution page on our website .