Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs

×

Error message

  • Notice: Undefined property: stdClass::$ds_changed in eval() (line 16 of /var/www/7/modules/php/php.module(80) : eval()'d code).
  • Notice: Undefined property: stdClass::$ss_search_api_url in eval() (line 20 of /var/www/7/modules/php/php.module(80) : eval()'d code).
  • Notice: Undefined property: stdClass::$tm_title in eval() (line 20 of /var/www/7/modules/php/php.module(80) : eval()'d code).
  • Notice: Undefined property: stdClass::$ds_changed in eval() (line 16 of /var/www/7/modules/php/php.module(80) : eval()'d code).
  • Notice: Undefined property: stdClass::$ss_search_api_url in eval() (line 20 of /var/www/7/modules/php/php.module(80) : eval()'d code).
  • Notice: Undefined property: stdClass::$tm_title in eval() (line 20 of /var/www/7/modules/php/php.module(80) : eval()'d code).
  • Notice: Undefined property: stdClass::$ds_changed in eval() (line 16 of /var/www/7/modules/php/php.module(80) : eval()'d code).
  • Notice: Undefined property: stdClass::$ss_search_api_url in eval() (line 20 of /var/www/7/modules/php/php.module(80) : eval()'d code).
  • Notice: Undefined property: stdClass::$tm_title in eval() (line 20 of /var/www/7/modules/php/php.module(80) : eval()'d code).
  • Notice: Undefined property: stdClass::$ds_changed in eval() (line 16 of /var/www/7/modules/php/php.module(80) : eval()'d code).
  • Notice: Undefined property: stdClass::$ss_search_api_url in eval() (line 20 of /var/www/7/modules/php/php.module(80) : eval()'d code).
  • Notice: Undefined property: stdClass::$tm_title in eval() (line 20 of /var/www/7/modules/php/php.module(80) : eval()'d code).

Aldec, Inc. , a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, has unveiled the latest release of Riviera-PRO, providing support for system simulation of Versal™ Adaptive Compute Acceleration Platform (ACAP) designs.

Metadata
Provider: 
Business Wire, Inc.Business Wire, Inc.
Retrieved on: 
Wednesday, June 14, 2023
Information
Tags: 
Electronic Design Automation, Engineering, Technology, Manufacturing, Software, Hardware, HBM, PS, Programmable logic device, RTL, UVM, Network on a chip, PL, QEMU, Vitis, HDL, SOC, Marketing, CCIX, SystemC, DMA, ACAP, IPS, AIE, Algorithm, Artificial intelligence, Architecture, Transaction processing system, Environment, SystemVerilog, Video game, FPGA
Geotags: 
UNITED STATES, NORTH AMERICA, CANADA, NEVADA, RIVIERA, INTERLAKEN
⚠ partially generated by AI ↴
Organisation: 
RIVIERA-PRO, ALDEC, ALDEC, INC., RIVIERA-PRO™
Summary
Key Points: 
  • Aldec, Inc. , a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, has unveiled the latest release of Riviera-PRO, providing support for system simulation of Versal™ Adaptive Compute Acceleration Platform (ACAP) designs.
  • Riviera-PRO supports system simulation of Versal ACAP designs based on the Vitis™ hardware emulation flow for testing the interactions between AIE, PS, and PL.
  • System simulation is highly critical for any Versal ACAP design because of its complex adaptable architecture and high-logic density.
  • System simulation can be used to perform algorithmic validation, verify architectural extrapolation, connected hardware platforms and application software.


Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, has unveiled the latest release of Riviera-PRO, providing support for system simulation of Versal™ Adaptive Compute Acceleration Platform (ACAP) designs.

Versal ACAP, developed by Xilinx/AMD, is a groundbreaking adaptable platform comprising an AI Engine (AIE), Processing System (PS), Programmable Logic (PL), Network on Chip (NoC) and hardened domain-specific IPs such as PCIe Gen5 with DMA and CCIX, HBM, 600G Interlaken and 600G Ethernet. Versal ACAP enables heterogeneous computing of complex algorithms and accelerates workloads, such as artificial intelligence, embedded computing, and high-performance computing.

Riviera-PRO supports system simulation of Versal ACAP designs based on the Vitis™ hardware emulation flow for testing the interactions between AIE, PS, and PL. The entire hardware emulation setup and system integration is done within the Vitis environment. Vitis runs the AIE simulator for the graph application, the Riviera-PRO simulator for the PL kernels, and QEMU (open-source system emulator) for the PS host application. SystemC models are also available for the AIE and NoC, and they can be simulated in Riviera-PRO too.

System simulation is highly critical for any Versal ACAP design because of its complex adaptable architecture and high-logic density. The full system design can be tested with full debug visibility much earlier in the project cycle without any physical hardware, making it easier to run more test scenarios, test corner cases, and debug complex problems.

Users can take advantage of Riviera-PRO’s high-performance mixed-HDL simulation engine, advanced debugging environment using waveform viewer, advanced dataflow, RTL hierarchy, objects viewer, and verification coverage features such as code coverage and functional coverage. Riviera-PRO’s comprehensive support for SystemVerilog and UVM is beneficial to users who need to develop reusable and complex testbench environments.

“The Versal ACAP architecture is revolutionary in the FPGA domain, and a game-changer for heterogeneous computing,” said Louie De Luna, Aldec’s Director of Marketing. “With Versal, users can customize their own domain-specific architectures for optimized computations of their specific workloads. We are now stepping into the computing era where the differentiation is done in hardware instead of software.”

The majority of FPGA projects are notorious for having at least one non-trivial bug escaping into production, and simulation-based verification is a key aspect in minimizing bug escapes. System simulation can be used to perform algorithmic validation, verify architectural extrapolation, connected hardware platforms and application software.

Several Versal ACAP tutorial designs and steps on how to use Riviera-PRO as the RTL simulator for the Vitis hardware emulation flow can be found on Aldec’s Github.

Riviera-PRO 2023.04 is now available for download and evaluation.

About Riviera-PRO™

Riviera-PRO™ addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. The tool enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest language and verification library standards.

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader and pioneer in Electronic Design Verification. Established in 1984, Aldec offers patented verification technology in the areas of mixed-language RTL simulation, FPGA-based acceleration and emulation, multi-FPGA partitioning and SoC/ASIC prototyping, design rule checking, clock domain crossing analysis, logic synthesis, RTAX/RTSX prototyping of radiation tolerant FPGAs for space applications, requirements traceability and functional verification for military, aerospace, avionics, automotive, medical, telecommunications and industrial applications. www.aldec.com

Copyright: 
Copyright Business Wire 2023