Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs
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Wednesday, June 14, 2023
Electronic Design Automation, Engineering, Technology, Manufacturing, Software, Hardware, HBM, PS, Programmable logic device, RTL, UVM, Network on a chip, PL, QEMU, Vitis, HDL, SOC, Marketing, CCIX, SystemC, DMA, ACAP, IPS, AIE, Algorithm, Artificial intelligence, Architecture, Transaction processing system, Environment, SystemVerilog, Video game, FPGA
Aldec, Inc. , a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, has unveiled the latest release of Riviera-PRO, providing support for system simulation of Versal™ Adaptive Compute Acceleration Platform (ACAP) designs.
Key Points:
- Aldec, Inc. , a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, has unveiled the latest release of Riviera-PRO, providing support for system simulation of Versal™ Adaptive Compute Acceleration Platform (ACAP) designs.
- Riviera-PRO supports system simulation of Versal ACAP designs based on the Vitis™ hardware emulation flow for testing the interactions between AIE, PS, and PL.
- System simulation is highly critical for any Versal ACAP design because of its complex adaptable architecture and high-logic density.
- System simulation can be used to perform algorithmic validation, verify architectural extrapolation, connected hardware platforms and application software.