Network on a chip

Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs

Retrieved on: 
Wednesday, June 14, 2023
Electronic Design Automation, Engineering, Technology, Manufacturing, Software, Hardware, HBM, PS, Programmable logic device, RTL, UVM, Network on a chip, PL, QEMU, Vitis, HDL, SOC, Marketing, CCIX, SystemC, DMA, ACAP, IPS, AIE, Algorithm, Artificial intelligence, Architecture, Transaction processing system, Environment, SystemVerilog, Video game, FPGA

Aldec, Inc. , a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, has unveiled the latest release of Riviera-PRO, providing support for system simulation of Versal™ Adaptive Compute Acceleration Platform (ACAP) designs.

Key Points: 
  • Aldec, Inc. , a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, has unveiled the latest release of Riviera-PRO, providing support for system simulation of Versal™ Adaptive Compute Acceleration Platform (ACAP) designs.
  • Riviera-PRO supports system simulation of Versal ACAP designs based on the Vitis™ hardware emulation flow for testing the interactions between AIE, PS, and PL.
  • System simulation is highly critical for any Versal ACAP design because of its complex adaptable architecture and high-logic density.
  • System simulation can be used to perform algorithmic validation, verify architectural extrapolation, connected hardware platforms and application software.

Kalray, Arteris, Secure-IC, and Thales, Win the Call for Projects Related to the AI Acceleration Strategy of the "France Relance 2030 - Future Investments" Plan

Retrieved on: 
Thursday, May 11, 2023
Hardware, Data Management, Technology, Artificial Intelligence, Software, Heart, Massively parallel processor array, DPU, Intellectual property, EPI, Investment, Telecommunications, Massively parallel, Internet of things, Network on a chip, European Processor Initiative, IP, Data processing unit, Plant, Data, Algorithm, Artificial intelligence, AI, Mobile phone, Medical device, Video game, Kalray, Thales of Miletus, European

Kalray's next-generation high-performance, low-power DPU processor is at the heart of the project.

Key Points: 
  • Kalray's next-generation high-performance, low-power DPU processor is at the heart of the project.
  • Use cases linked to artificial intelligence (AI) are developing exponentially.
  • This technological leadership enables Kalray to offer a serious French and European alternative to the predominantly American or Chinese technology players.
  • "In the current geopolitical context, the semiconductor industry has become essential, both in terms of production tools and technological know-how for designing processors.

Arteris Announces Financial Results for the First Quarter 2023 and Estimated Second Quarter and Full Year 2023 Guidance

Retrieved on: 
Thursday, May 4, 2023
Intellectual property, Partnership, Arteris, Enterprise (computer), Original equipment manufacturer, Network on a chip, SOC, IP, HiSilicon, Phase 10, TTM, ACV, Machine learning, Socs, Consumer, AI, OEM, DJI, Automation, Mobile phone, Beauty salon, Automotive industry

CAMPBELL, Calif., May 04, 2023 (GLOBE NEWSWIRE) -- Arteris, Inc. (Arteris or Arteris IP), a leading provider of network-on-chip (NoC) interconnect and other intellectual property (IP) technology that manages the on-chip communications in system-on-chip (SoC) semiconductor devices, today announced financial results for the first quarter ended March 31, 2023 as well as estimated second quarter and full year 2023 guidance.

Key Points: 
  • CAMPBELL, Calif., May 04, 2023 (GLOBE NEWSWIRE) -- Arteris, Inc. (Arteris or Arteris IP), a leading provider of network-on-chip (NoC) interconnect and other intellectual property (IP) technology that manages the on-chip communications in system-on-chip (SoC) semiconductor devices, today announced financial results for the first quarter ended March 31, 2023 as well as estimated second quarter and full year 2023 guidance.
  • “We’re excited to report a solid start to the year, with Annual Contract Value plus Trailing-Twelve-Month Royalties of $54.8 million, up 20% year-over-year when adjusted to exclude HiSilicon and DJI and up 5% sequentially,” said K. Charles Janac, President and CEO of Arteris.
  • In addition to automotive, we continue to see strong demand from AI and Machine Learning applications which increasingly require network-on-chip IP and benefit from SoC integration automation.
  • Estimated Second Quarter and Full Year 2023 Guidance:

Tenstorrent Selects Arteris IP for AI High-Performance Computing and Datacenter RISC-V Chiplets

Retrieved on: 
Tuesday, May 2, 2023
Communication, AIP, Arteris, Network on a chip, Deep learning, ML, SOC, IP, QOS, CPU, AI, Video game

CAMPBELL, Calif., May 02, 2023 (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced Tenstorrent has licensed Ncore and FlexNoC interconnect IP for its AI chiplet systems.

Key Points: 
  • CAMPBELL, Calif., May 02, 2023 (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced Tenstorrent has licensed Ncore and FlexNoC interconnect IP for its AI chiplet systems.
  • Tenstorrent combines AI and RISC-V computing together to deliver highly customized, high-performance chiplet and computing solutions that are tailored to specific workloads and applications.
  • “We are happy to share that we are partnering with Arteris to use Ncore and FlexNoC IP in our next-generation product," said Jim Keller, CEO of Tenstorrent.
  • The Arteris team and IP solved our on-chip network problems so we can focus on building our next-generation AI and RISC-V CPU products."

Arteris IP Licensed by Axelera AI to Accelerate Computer Vision at the Edge

Retrieved on: 
Wednesday, April 26, 2023
Acceleration, AIP, LPDDR4X, Network on a chip, PCI Express, SOC, IP, Metris, Machine learning, Workload, Architecture, AHB, Silicon, Metis, Automation, Medical device, Arteris

The Arteris IP will be used for SoC connectivity in the Metis AI platform, a hardware and software platform for computer vision AI inference at the edge.

Key Points: 
  • The Arteris IP will be used for SoC connectivity in the Metis AI platform, a hardware and software platform for computer vision AI inference at the edge.
  • The Metis AI processing unit (AIPU), as part of the Metris AI Platform, is equipped with four homogeneous AI cores built for complete neural network inference acceleration.
  • “We are honored to be working with Axelera AI on the edge AI inferencing in computer vision applications,” said K. Charles Janac, president and CEO of Arteris.
  • “This further supports the leading role that Arteris plays in accelerating AI innovation across a broad list of end applications.”

Introducing Signature IP Corporation – Providing a Configurable And Flexible Platform for SoC Development

Retrieved on: 
Wednesday, March 15, 2023
Technology, Electronic Design Automation, Semiconductor, Transfer, Spirit level, Signature, Architecture, Inoculation, Software as a service, SOC, RTL, Network on a chip, Silicon, IP, National Oceanography Centre, Southampton, Video game

Signature IP Corporation, a startup focused on providing a configurable and flexible platform for System-on-Chip (SoC) development, today officially launched the company and publicly announced availability of its first products.

Key Points: 
  • Signature IP Corporation, a startup focused on providing a configurable and flexible platform for System-on-Chip (SoC) development, today officially launched the company and publicly announced availability of its first products.
  • Signature IP’s initial products are focused on fast and flexible implementation of Networks-on-Chip (NoCs), with future products enabling a platform-based approach to SoC development which is physically-aware and NoC-aware, delivering industry-standard interfaces and interconnect within and between silicon dies.
  • “Signature IP was founded with the purpose to make it easy to design and configure the NoC backbone within a chip and benefit from the flexibility of exploring the design space before committing to an architecture,” said Purna Mohanty, CEO of Signature IP Corporation.
  • For more information about Signature IP products, please visit https://www.signatureip.ai/ .

Arteris Announces Financial Results for the Fourth Quarter and Full Year 2022 and Estimated First Quarter and Full Year 2023 Guidance

Retrieved on: 
Tuesday, February 28, 2023
Overalls, RPO, Network on a chip, Partnership, Acquisition, TTM, Telechips, Economics, Growth, ACV, HSI, Intellectual property, Machine learning, HiSilicon, BIS, DJI, SiFive, Arteris, Cryptocurrency, Bank, Video game, Flag semaphore, SOC

CAMPBELL, Calif., Feb. 28, 2023 (GLOBE NEWSWIRE) -- Arteris, Inc. (Arteris or Arteris IP), a leading provider of network-on-chip (NoC) interconnect and other intellectual property (IP) technology that manages the on-chip communications in system-on-chip (SoC) semiconductor devices, today announced financial results for the fourth quarter and year ended December 31, 2022, and provided estimated first quarter and full year 2023 guidance.

Key Points: 
  • CAMPBELL, Calif., Feb. 28, 2023 (GLOBE NEWSWIRE) -- Arteris, Inc. (Arteris or Arteris IP), a leading provider of network-on-chip (NoC) interconnect and other intellectual property (IP) technology that manages the on-chip communications in system-on-chip (SoC) semiconductor devices, today announced financial results for the fourth quarter and year ended December 31, 2022, and provided estimated first quarter and full year 2023 guidance.
  • “We’re excited to report a strong finish to 2022, with Annual Contract Value plus Trailing Twelve Month Royalties of $52.4 million, an increase of 22% year-over-year when adjusted for the loss of HiSilicon and DJI, which can be attributed to tighter BIS restrictions after 2019,” said K. Charles Janac, President and CEO of Arteris IP.
  • “With the introduction of our new FlexNoC 5 innovation and the acquisition of Semifore in the fourth quarter, we are working to enable our customers to accelerate their SoC design and improve the overall SoC design economics while shortening product schedules and the risks of costly redesigns.
  • Estimated First Quarter and Full Year 2023 Guidance:

TRUECHIP ANNOUNCES EARLY ADOPTER VERSION OF SUB-SYSTEM VERIFICATION IP

Retrieved on: 
Tuesday, February 28, 2023
SS, Creativity, Network on a chip, ASIC, FPGA, Organization, Silicon, RISC, Semiconductor intellectual property core, Automation, AI, Regression, SAN, DUT, Artificial intelligence, IPS, Map, SOC, VIP, GUI, Artificiality, Verification, Microcontroller, Memory, Very important person, Regression analysis, Audit, Security printing, Computer data storage, Automotive industry, Defense, Network

SAN JOSE, Calif. and BENGALURU, India, Feb. 28, 2023 /PRNewswire/ -- Truechip , the Verification IP Specialist, announced that it has launched an early adopter version of Sub-system Verification IP (SS VIP).

Key Points: 
  • SAN JOSE, Calif. and BENGALURU, India, Feb. 28, 2023 /PRNewswire/ -- Truechip , the Verification IP Specialist, announced that it has launched an early adopter version of Sub-system Verification IP (SS VIP).
  • A sub-system level verification reduces the verification cycle time as it requires much lesser run time compared to SOC Verification.
  • Speaking at DVCON US, held at San Jose, California, Nitin Kishore, CEO, Truechip, said, "The launch of Sub-System Verification IP is another step towards macro level verification.
  • Last year we came up with NoC Verification IP which helps to automate the verification of any NoC DUT.

Arteris and SiFive Partner to Accelerate RISC-V SoC Design of Edge AI Applications

Retrieved on: 
Monday, February 27, 2023
Network on a chip, Partnership, Linux, Socs, AIP, National Oceanography Centre, Southampton, AI, AMD, Acceleration, SOC, Electronics, SiFive, IP, Freedom, SDK, Arteris, Mobile phone, Video game

CAMPBELL, Calif. and SANTA CLARA, Calif., Feb. 27, 2023 (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, and SiFive, Inc., the founder and leader of RISC-V computing, today announced their partnership to help speed up Edge AI electronic product innovation for consumer electronics and industrial applications.

Key Points: 
  • The combination of the SiFive Intelligence™ processor IP and Arteris Ncore interconnect IP accelerates the path for customers to realize Edge AI SoCs.
  • SiFive Intelligence X280, a multi-core capable RISC-V processor, provides a unique blend of performance, power efficiency, and an intuitive programming model, and enables various data-driven applications, including AI inference, image processing, data center acceleration and other use cases.
  • Arteris Ncore cache coherent interconnect IP is a configurable and scalable network-on-chip (NoC) interconnect for heterogeneous cache coherent systems-on-chip (SoCs).
  • SiFive also provides the Freedom SDK for Linux for software development with SiFive IP.

Arteris Unveils Next-Generation FlexNoC 5 Physically Aware Network-on-Chip IP

Retrieved on: 
Wednesday, February 22, 2023
Network on a chip, IEEE, AIP, Arm, IP-XACT, SOC, RTL, IP, PPA, Arteris, Video game, Management

CAMPBELL, Calif., Feb. 22, 2023 (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced the launch of Arteris FlexNoC 5 physically aware network-on-chip (NoC) interconnect IP. FlexNoC 5 enables SoC architecture teams, logic designers and integrators to incorporate physical constraint management across power, performance and area (PPA) to deliver a physically aware IP connecting the SoC. This technology enables 5X faster physical convergence over manual refinements with fewer iterations from the layout team for automotive, communications, consumer electronics, enterprise computing, and industrial applications.

Key Points: 
  • CAMPBELL, Calif., Feb. 22, 2023 (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced the launch of Arteris FlexNoC 5 physically aware network-on-chip (NoC) interconnect IP.
  • FlexNoC 5 enables SoC architecture teams, logic designers and integrators to incorporate physical constraint management across power, performance and area (PPA) to deliver a physically aware IP connecting the SoC.
  • “Sondrel has deployed Arteris FlexNoC interconnect IP across several customer SoC projects to great effect,” said Graham Curren, CEO of Sondrel.
  • “With FlexNoC 5, we consider physical effects early in the process, delivering physically aware NoC IP which helps customers meet PPA goals and execute SoC projects on schedule and budget.”